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/ AmigActive 10 / AACD 10.iso / AACD / Games / MAME / src / machine / namcos2.h < prev    next >
C/C++ Source or Header  |  2000-05-25  |  10KB  |  304 lines
  1. /***************************************************************************
  2.  
  3.   namcos2.h
  4.  
  5.   Common functions & declarations for the Namco System 2 driver
  6.  
  7. ***************************************************************************/
  8.  
  9. // #define NAMCOS2_DEBUG_MODE
  10.  
  11.  
  12. /* CPU reference numbers */
  13.  
  14. #define NAMCOS2_CPU1    0
  15. #define NAMCOS2_CPU2    1
  16. #define NAMCOS2_CPU3    2
  17. #define NAMCOS2_CPU4    3
  18.  
  19. #define CPU_MASTER    NAMCOS2_CPU1
  20. #define CPU_SLAVE    NAMCOS2_CPU2
  21. #define CPU_SOUND    NAMCOS2_CPU3
  22. #define CPU_MCU     NAMCOS2_CPU4
  23.  
  24. /* VIDHRDW */
  25.  
  26. #define GFX_OBJ1    0
  27. #define GFX_OBJ2    1
  28. #define GFX_CHR     2
  29. #define GFX_ROZ     3
  30.  
  31. /*********************************************/
  32. /* IF GAME SPECIFIC HACKS ARE REQUIRED THEN  */
  33. /* USE THE namcos2_gametype VARIABLE TO FIND */
  34. /* OUT WHAT GAME IS RUNNING                  */
  35. /*********************************************/
  36.  
  37. #define NAMCOS2_ASSAULT             0x1000
  38. #define NAMCOS2_ASSAULT_JP            0x1001
  39. #define NAMCOS2_ASSAULT_PLUS        0x1002
  40. #define NAMCOS2_BUBBLE_TROUBLE        0x1003
  41. #define NAMCOS2_BURNING_FORCE        0x1004
  42. #define NAMCOS2_COSMO_GANG            0x1005
  43. #define NAMCOS2_COSMO_GANG_US        0x1006
  44. #define NAMCOS2_DIRT_FOX            0x1007
  45. #define NAMCOS2_DIRT_FOX_JP         0x1008
  46. #define NAMCOS2_DRAGON_SABER        0x1009
  47. #define NAMCOS2_DRAGON_SABER_JP     0x100a
  48. #define NAMCOS2_FINAL_LAP            0x100b
  49. #define NAMCOS2_FINAL_LAP_2         0x100c
  50. #define NAMCOS2_FINAL_LAP_3         0x100d
  51. #define NAMCOS2_FINEST_HOUR         0x100e
  52. #define NAMCOS2_FOUR_TRAX            0x100f
  53. #define NAMCOS2_GOLLY_GHOST         0x1010
  54. #define NAMCOS2_LUCKY_AND_WILD        0x1011
  55. #define NAMCOS2_MARVEL_LAND         0x1012
  56. #define NAMCOS2_METAL_HAWK            0x1013
  57. #define NAMCOS2_MIRAI_NINJA         0x1014
  58. #define NAMCOS2_ORDYNE                0x1015
  59. #define NAMCOS2_PHELIOS             0x1016
  60. #define NAMCOS2_ROLLING_THUNDER_2    0x1017
  61. #define NAMCOS2_STEEL_GUNNER        0x1018
  62. #define NAMCOS2_STEEL_GUNNER_2        0x1019
  63. #define NAMCOS2_SUPER_WSTADIUM        0x101a
  64. #define NAMCOS2_SUPER_WSTADIUM_92    0x101b
  65. #define NAMCOS2_SUPER_WSTADIUM_93    0x101c
  66. #define NAMCOS2_SUZUKA_8_HOURS        0x101d
  67. #define NAMCOS2_SUZUKA_8_HOURS_2    0x101e
  68. #define NAMCOS2_VALKYRIE            0x101f
  69. #define NAMCOS2_KYUUKAI_DOUCHUUKI    0x1020
  70.  
  71. extern int namcos2_gametype;
  72.  
  73. /*********************************************/
  74.  
  75. int  namcos2_vh_start(void);
  76. void namcos2_vh_stop(void);
  77. void namcos2_vh_update_default(struct osd_bitmap *bitmap, int full_refresh);
  78. void namcos2_vh_update_finallap(struct osd_bitmap *bitmap, int full_refresh);
  79. void namcos2_vh_convert_color_prom(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
  80.  
  81. /* MACHINE */
  82.  
  83. void namcos2_init_machine(void);
  84.  
  85.  
  86. /**************************************************************/
  87. /* Dual port memory handlers                                  */
  88. /**************************************************************/
  89. READ_HANDLER( namcos2_dpram_byte_r );
  90. WRITE_HANDLER( namcos2_dpram_byte_w );
  91. READ_HANDLER( namcos2_68k_dpram_word_r );
  92. WRITE_HANDLER( namcos2_68k_dpram_word_w );
  93.  
  94. extern unsigned char *namcos2_dpram;
  95.  
  96. /**************************************************************/
  97. /* Sprite memory handlers                                      */
  98. /**************************************************************/
  99. WRITE_HANDLER( namcos2_68k_sprite_ram_w );
  100. WRITE_HANDLER( namcos2_68k_sprite_bank_w );
  101. READ_HANDLER( namcos2_68k_sprite_ram_r );
  102. READ_HANDLER( namcos2_68k_sprite_bank_r );
  103.  
  104. extern unsigned char *namcos2_sprite_ram;
  105. extern int namcos2_sprite_bank;
  106.  
  107.  
  108. /**************************************************************/
  109. /*    EEPROM memory function handlers                           */
  110. /**************************************************************/
  111. #define NAMCOS2_68K_EEPROM_W    namcos2_68k_eeprom_w, &namcos2_eeprom, &namcos2_eeprom_size
  112. #define NAMCOS2_68K_EEPROM_R    namcos2_68k_eeprom_r
  113. void    namcos2_nvram_handler(void *file, int read_or_write);
  114. WRITE_HANDLER(     namcos2_68k_eeprom_w );
  115. READ_HANDLER(     namcos2_68k_eeprom_r );
  116. extern unsigned char *namcos2_eeprom;
  117. extern size_t namcos2_eeprom_size;
  118.  
  119. /**************************************************************/
  120. /*    Shared video memory function handlers                      */
  121. /**************************************************************/
  122. WRITE_HANDLER( namcos2_68k_vram_w );
  123. READ_HANDLER( namcos2_68k_vram_r );
  124.  
  125. extern size_t namcos2_68k_vram_size;
  126.  
  127. READ_HANDLER( namcos2_68k_vram_ctrl_r );
  128. WRITE_HANDLER( namcos2_68k_vram_ctrl_w );
  129.  
  130. extern unsigned char namcos2_68k_vram_ctrl[];
  131.  
  132. extern struct tilemap *namcos2_tilemap0;
  133. extern struct tilemap *namcos2_tilemap1;
  134. extern struct tilemap *namcos2_tilemap2;
  135. extern struct tilemap *namcos2_tilemap3;
  136. extern struct tilemap *namcos2_tilemap4;
  137. extern struct tilemap *namcos2_tilemap5;
  138.  
  139. extern int namcos2_tilemap0_flip;
  140. extern int namcos2_tilemap1_flip;
  141. extern int namcos2_tilemap2_flip;
  142. extern int namcos2_tilemap3_flip;
  143. extern int namcos2_tilemap4_flip;
  144. extern int namcos2_tilemap5_flip;
  145.  
  146. /**************************************************************/
  147. /*    Shared video palette function handlers                      */
  148. /**************************************************************/
  149. READ_HANDLER( namcos2_68k_video_palette_r );
  150. WRITE_HANDLER( namcos2_68k_video_palette_w );
  151.  
  152. #define NAMCOS2_COLOUR_CODES    0x20
  153. extern unsigned char *namcos2_68k_palette_ram;
  154. extern size_t namcos2_68k_palette_size;
  155.  
  156.  
  157. /**************************************************************/
  158. /*    Shared data ROM memory handlerhandlers                      */
  159. /**************************************************************/
  160. READ_HANDLER( namcos2_68k_data_rom_r );
  161.  
  162.  
  163. /**************************************************************/
  164. /* Shared serial communications processory (CPU5 ????)          */
  165. /**************************************************************/
  166. READ_HANDLER( namcos2_68k_serial_comms_ram_r );
  167. WRITE_HANDLER( namcos2_68k_serial_comms_ram_w );
  168. READ_HANDLER( namcos2_68k_serial_comms_ctrl_r );
  169. WRITE_HANDLER( namcos2_68k_serial_comms_ctrl_w );
  170.  
  171. extern unsigned char  namcos2_68k_serial_comms_ctrl[0x10];
  172. extern unsigned char *namcos2_68k_serial_comms_ram;
  173.  
  174.  
  175.  
  176. /**************************************************************/
  177. /* Shared protection/random number generator                  */
  178. /**************************************************************/
  179. READ_HANDLER( namcos2_68k_key_r );
  180. WRITE_HANDLER( namcos2_68k_key_w );
  181.  
  182. extern unsigned char namcos2_68k_key[];
  183.  
  184. READ_HANDLER( namcos2_68k_protect_r );
  185. WRITE_HANDLER( namcos2_68k_protect_w );
  186.  
  187. extern int namcos2_68k_protect;
  188.  
  189.  
  190.  
  191. /**************************************************************/
  192. /* Non-shared memory custom IO device - IRQ/Inputs/Outputs     */
  193. /**************************************************************/
  194.  
  195. #define NAMCOS2_C148_0            0        /* 0x1c0000 */
  196. #define NAMCOS2_C148_1            1
  197. #define NAMCOS2_C148_2            2
  198. #define NAMCOS2_C148_CPUIRQ     3
  199. #define NAMCOS2_C148_EXIRQ        4        /* 0x1c8000 */
  200. #define NAMCOS2_C148_POSIRQ     5
  201. #define NAMCOS2_C148_SERIRQ     6
  202. #define NAMCOS2_C148_VBLANKIRQ    7
  203.  
  204. extern int    namcos2_68k_master_C148[32];
  205. extern int    namcos2_68k_slave_C148[32];
  206.  
  207. WRITE_HANDLER( namcos2_68k_master_C148_w );
  208. READ_HANDLER( namcos2_68k_master_C148_r );
  209. int  namcos2_68k_master_vblank( void );
  210. void namcos2_68k_master_posirq( int moog );
  211.  
  212. WRITE_HANDLER( namcos2_68k_slave_C148_w );
  213. READ_HANDLER( namcos2_68k_slave_C148_r );
  214. int  namcos2_68k_slave_vblank(void);
  215. void namcos2_68k_slave_posirq( int moog );
  216.  
  217.  
  218. /**************************************************************/
  219. /* MASTER CPU RAM MEMORY                                      */
  220. /**************************************************************/
  221.  
  222. extern unsigned char *namcos2_68k_master_ram;
  223.  
  224. #define NAMCOS2_68K_MASTER_RAM_W    MWA_BANK3, &namcos2_68k_master_ram
  225. #define NAMCOS2_68K_MASTER_RAM_R    MRA_BANK3
  226.  
  227.  
  228. /**************************************************************/
  229. /* SLAVE CPU RAM MEMORY                                       */
  230. /**************************************************************/
  231.  
  232. extern unsigned char *namcos2_68k_slave_ram;
  233.  
  234. #define NAMCOS2_68K_SLAVE_RAM_W     MWA_BANK4, &namcos2_68k_slave_ram
  235. #define NAMCOS2_68K_SLAVE_RAM_R     MRA_BANK4
  236.  
  237.  
  238. /**************************************************************/
  239. /*    ROZ - Rotate & Zoom memory function handlers              */
  240. /**************************************************************/
  241.  
  242. WRITE_HANDLER( namcos2_68k_roz_ctrl_w );
  243. READ_HANDLER( namcos2_68k_roz_ctrl_r );
  244. extern unsigned char namcos2_68k_roz_ctrl[];
  245.  
  246. WRITE_HANDLER( namcos2_68k_roz_ram_w );
  247. READ_HANDLER( namcos2_68k_roz_ram_r );
  248. extern size_t namcos2_68k_roz_ram_size;
  249. extern unsigned char *namcos2_68k_roz_ram;
  250.  
  251.  
  252. /**************************************************************/
  253. /* FINAL LAP road generator definitions.....                  */
  254. /**************************************************************/
  255.  
  256. WRITE_HANDLER( namcos2_68k_roadtile_ram_w );
  257. READ_HANDLER( namcos2_68k_roadtile_ram_r );
  258. extern unsigned char *namcos2_68k_roadtile_ram;
  259. extern size_t namcos2_68k_roadtile_ram_size;
  260.  
  261. WRITE_HANDLER( namcos2_68k_roadgfx_ram_w );
  262. READ_HANDLER( namcos2_68k_roadgfx_ram_r );
  263. extern unsigned char *namcos2_68k_roadgfx_ram;
  264. extern size_t namcos2_68k_roadgfx_ram_size;
  265.  
  266. WRITE_HANDLER( namcos2_68k_road_ctrl_w );
  267. READ_HANDLER( namcos2_68k_road_ctrl_r );
  268.  
  269.  
  270. /**************************************************************/
  271. /*                                                              */
  272. /**************************************************************/
  273. #define BANKED_SOUND_ROM_R        MRA_BANK6
  274. #define CPU3_ROM1                6            /* Bank number */
  275.  
  276.  
  277.  
  278. /**************************************************************/
  279. /* Sound CPU support handlers - 6809                          */
  280. /**************************************************************/
  281.  
  282. int  namcos2_sound_interrupt(void);
  283. WRITE_HANDLER( namcos2_sound_bankselect_w );
  284.  
  285.  
  286. /**************************************************************/
  287. /* MCU Specific support handlers - HD63705                      */
  288. /**************************************************************/
  289.  
  290. int  namcos2_mcu_interrupt(void);
  291.  
  292. WRITE_HANDLER( namcos2_mcu_analog_ctrl_w );
  293. READ_HANDLER( namcos2_mcu_analog_ctrl_r );
  294.  
  295. WRITE_HANDLER( namcos2_mcu_analog_port_w );
  296. READ_HANDLER( namcos2_mcu_analog_port_r );
  297.  
  298. WRITE_HANDLER( namcos2_mcu_port_d_w );
  299. READ_HANDLER( namcos2_mcu_port_d_r );
  300.  
  301. READ_HANDLER( namcos2_input_port_0_r );
  302. READ_HANDLER( namcos2_input_port_10_r );
  303. READ_HANDLER( namcos2_input_port_12_r );
  304.